1. Field of the Invention
This invention relates to a semiconductor memory device with memory cells each including a charge accumulation layer and a control gate and a method of reading data in the memory device. More particularly, this invention relates to a nonvolatile semiconductor memory device including MOS transistors each having a floating gate and a control gate.
2. Description of the Related Art
In recent years, semiconductor memory devices, particularly memory cells for holding data, have been miniaturized further. As the size of a memory cell decreases, the cell current flowing through the bit line in reading data decreases. This causes a problem: the data read time becomes longer.
To solve this problem, various sense amplifiers capable of a high-speed operation even if the cell current decreases have been disclosed in, for example, Jpn. Pat. Appln. KOKAI Publication No. 2002-230989, Jpn. Pat. Appln. KOKAI Publication No. 2000-090669, and U.S. Pat. No. 6,091,629. However, each of the sense amplifiers compares a reference current with the cell current, thereby amplifying the data. Accordingly, a reference current generator circuit is required, which causes a problem: the size of the semiconductor memory becomes larger.